1. Field of the Invention
This invention relates generally to ESD protection circuits, and more particularly, to ESD protection circuits having a controlled breakdown voltage.
2. Description of the Related Art
Integrated circuits utilize protection circuits to prevent damage from excessive voltage caused by electrostatic discharge (ESD) or power supply overvoltage events. Prior art protection circuits typically utilize reverse-biased diodes acting as avalanche breakdown xe2x80x9cclampsxe2x80x9d as shown in FIG. 1 to limit the voltage between the power supply terminals of an integrated circuit (IC). However, a problem with using a reverse-biased diode as a clamp is that the breakdown voltage of the diode can vary widely depending on the IC fabrication process and the design approach used to build the junction. Under some process conditions, the diode voltage under ESD conditions can approach 50-70 volts, which is much too high to protect the IC.
Another approach to providing ESD protection involves the use of an avalanche transistor with a floating base terminal as shown in FIG. 2. This circuit relies on the BVCEO of the avalanche transistor which, for a large NPN transistor fabricated using a contemporary RF processes, is typically about 7 volts. When used in this configuration, any leakage current across the base-collector junction, as well as any current driven into the base from the base-emitter junction, is multiplied by impact-ionization in the high-field region in the reverse-biased base-collector junction""s depletion region. The fact that none of the current in the base is siphoned off through the base terminal, but instead is subject to xcex2-multiplication in the base-emitter junction, serves to reduce the BVCBO, which is typically about 15-17 volts, down to a BVCEO of about 7 volts.
Although the avalanche transistor of FIG. 2 typically provides a lower avalanche breakdown voltage than a reverse-biased diode, the BVCEO is a strong function of process-related parameters such as IS, xcex2F, temperature, hot electron effects, doping profiles, etc., which make it highly variable. Thus, the transistor in a modem IC process can break down during normal operation if a power supply transient occurs, especially if the circuit is used with a 5.5 volt supply.
In one embodiment of the present invention, an ESD protection circuit utilizes a base-emitter resistor to remove charge from an avalanche transistor, thereby providing a measure of control over the breakdown voltage which can be adjusted by varying the value of the base-emitter resistor.
In another embodiment of the present invention, an ESD protection circuit utilizes one or more diodes connected in series with an avalanche transistor for increasing the voltage across the protection circuit when the transistor avalanches, thereby increasing the margin between the avalanche voltage and the normal operating voltage.
In a further embodiment of the present invention, an ESD protection circuit utilizes a trigger network coupled to an avalanche transistor for driving the transistor so as to trigger avalanche when the voltage across the ESD protection circuit reaches a trigger voltage. In one embodiment, the trigger network includes a string of diodes coupled between the collector and base of the avalanche transistor. When the voltage across the trigger network reaches a predetermined value at which the diodes are forward biased to conduct a significant amount of current, the network begins supplying base current to the transistor, thereby triggering avalanche. The trigger voltage can be programmed by adjusting the number of diodes, or by adjusting the breakdown voltage of one or more reverse-biased zener diodes used in place of one or more of the normal diodes in another embodiment. A base-emitter resistor prevents false triggering by removing leakage charge from the base of the transistor. A base resistor coupled in series with the transistor limits the removal of charge under avalanche conditions, thereby causing the avalanche to be self-sustaining once initiated by the trigger network. One or more forward-biased diodes can be coupled in series with the transistor to increase the voltage across the protection circuit during avalanche.
An advantage of the present invention is that it provides improved control of the breakdown voltage of an ESD protection network.
Another advantage of the present invention is that it provides immunity from the process-dependent values of BVCEO and BVCBO of an avalanche transistor.
A further advantage of the present invention is that it provides immunity from false discharge due to leakage current.